The power dissipation is 14 mW at 2. Experimental results show that an 84 dB dynamic range is achieved over a 1. This proposed structure will be potentially useful for low-impendence low-power audio applications. A prototype chip has been designed and fabricated in a 0. This paper presents the design and experimental results of a 0.
The new technique exhibits improvement over other existing techniques. The technique is based on a single differential pair, avoiding the issues associated with complimentary pair techniques, such as the degradation of common-mode rejection ratio and signal-dependent input referred offset. The power dissipation is 14mW at 2. A prototype chip is fabricated in a 0. The accuracy of calibration is not limited by mismatch of charge injections. The trend toward high frequency and broadband digital communication has increased the demand for low jitter, low phase noise clock generation circuits. Simulation results show that this modulator can reach 14b performance with only about 15mWpower consumptions This paper proposes a digital background calibration method that mitigates the effects of errors of 2nd order analog loop filter in multi-bit cascaded sigma-delta modulators.
Finally, we propose a novel technique which achieves within,variation over the full input common-mode voltage range. Comparison with continuous gm tuning and some other passive tuning implementations is also presented. The passive integrators save power, and introduce no distortion. When we look at telecommunication standards of the past, present and the future, we notice a continued trend from narrow band specifications to wide band ones, with higher carrier frequency Fig. Theoretical analysis along with simulation results are discussed to demonstrate the performance of each constant- technique.
Simulations show that, when the input common-mode voltage swings from rail to rail, the Op Amp's input stage varies around and , respectively, for input transistors in the strong and weak inversion regions. Very small variations less than have been achieved without sacrificing the large-signal behavior. A novel static feedback loop is employed to minimize the N and P transconductance mismatch due to process and temperature variations. Passive networks do not consume power, introduce no distortions. Robustness against noise and mismatch are the main advantage of the conventional latch type comparator. The second architecture generates a left-half-plane zero to further improve the phase margin.
However, it suffers from high sufficient power supply, which is caused by many stacked transistor in circuit design. The simulation results showed constant-gm plusmn0. The remainder of this paper is organized as follows. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A prototype chip was designed for a 0. The out-of-band test tone can be easily removed by a decimation filter, therefore background calibration is possible. The gm variation of the input stage is within ±3% from rail-to-rail.
In contrast to traditional continuous-time delta-sigma modulators, this design utilizes passive networks, consisting of only resistors and capacitors, to perform part of the functions of loop filters. To overcome this limitation, we invented a time-splitting subranging architecture. Experimental results show that 84dB dynamic range is achieved with the 1. The output currents of the N and P differential pairs are dynamically steered to keep a constant gm and a constant slew rate. A circuit is designed in 0.
Reduction of power consumption is achieved by sharing amplifiers. Both techniques employ double feedforward paths to remove the right-half-plane zero. We present a 5th -order continuous-time SigmaDelta modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The proposed scheme is verified by the experimental results of a test chip in a 0. The prototype chip is designed in a 0. The pros and cons of each technique are discussed. Based on the proposed technique, a 1.
A low power, high bandwidth continuous-time delta-sigma modulator is proposed in this paper. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. The input offset voltage of the amplifier is eliminated by swapping the differential inputs and outputs of the amplifier. A novel signal and reference sampling network eliminates input common-mode voltages and relaxes op-amp linearity requirements, making it possible to use short channel length transistors for speed and power efficiency. The active integrators provide gain and minimize internal noise contributions. Sufficient power supply rejection is maintained through the biasing circuit. With a 3-V supply, the gm variation is kept within ±1% under nominal conditions and ±3% when there is ±40% mismatch of input transistor transconductance parameters.
A prototype chip was designed for 0. For similar performance, considerable power can be saved. A constant-gm input stage, which features both constant small-signal and large-signal behavior over the entire input common-mode range, is proposed in this paper. A novel capacitive level shifter keeps the effective input common-mode voltage constant, without attenuating the differential-mode voltage. The differential amplifier based on the bipolar junction transistors, which operate at high-current density, is analysed in the work.